Preliminary / Target (pre-silicon).Every specification on this page is a design target from the MCN-1 specification, Rev A0, and is subject to change prior to production release.
Secure wireless MCU
MCN-1
A multi-core 32-bit RISC-V wireless microcontroller in pre-silicon
development: dual-band Wi-Fi 6 and Bluetooth 5.4 LE +
Classic radio, a hardware security subsystem with a PUF-based
root of trust, and a full embedded peripheral set on a single die.
Two application cores at 400 MHz with hardware FPU and
bit-manipulation, plus an always-on 80 MHz security core on
its own ultra-low-power island. 1.6 DMIPS/MHz per core,
4-stage in-order pipeline. target
Radio
Wi-Fi 6 + Bluetooth 5.4
Dual-band 802.11ax 1×1 with OFDMA, TWT, and WPA3, plus
Bluetooth 5.4 LE + Classic with LE Audio and LE Long Range.
Per-association Wi-Fi keys are derived in the secure subsystem.
target
Two-world (secure / normal) execution is enforced by PMP + ePMP and
a per-transaction world-ID bit on the system bus. The security core
runs the security monitor, secure boot, and cryptographic services
in the secure world.
CPU subsystem — preliminary pre-silicon targets target
Application cores
2× RV32IMACFB_Zkn_Zks
Application core frequency
400 MHz (max)
Security / ULP core
1× RV32IMC_Zk, always-on island
Security core frequency
80 MHz (max)
Pipeline
4-stage, in-order
Performance
1.6 DMIPS/MHz per core
FPU
Single-precision IEEE-754 (F extension)
ISA extensions
I, M, A, C, F, B (bit-manip), Zkn/Zks (scalar crypto), Zkr (entropy)
Memory protection
PMP / Smepmp, 16 regions per core
DMA isolation
IOPMP on all DMA-capable masters
Interrupt controller
RISC-V PLIC + CLIC
Debug
RISC-V Debug Module (JTAG)
02 · Memory
Memory
Memory regions — preliminary pre-silicon targets target
Region
Size
Notes
Boot ROM
32 KB
Immutable mask ROM
Secure SRAM
32 KB
Secure-world only
Main SRAM
512 KB
PMP-partitioned
L1 cache (per app core)
32 KB I + 16 KB D
—
In-package flash (option)
4 / 8 / 16 MB
AES-XTS at rest; key derived from PUF
In-package PSRAM (option)
4 / 8 MB
AES-XTS at rest; ECC protected
eFuse (OTP)
4 KB
Provisioning data, region lock, debug lock
03 · Security
Security subsystem
Root of trust target
Device identity
PUF-based per-die unique seed
Entropy source
TRNG, oscillator-based, NIST SP 800-90B/C with on-line health tests; 3 Mbps post-conditioning
Key storage
4 KB OTP eFuse + 32 KB secure SRAM behind PMP and the security monitor
Boot ROM
32 KB immutable, deterministic build
Boot & attestation target
Boot chain
Multi-stage, ROM-anchored
Bootloader signature
Ed25519 + Dilithium-3 hybrid
Firmware image protection
Kyber-768 KEM-wrapped key + AES-256-GCM
Measurement
SHA-3-384 extended into on-die PCRs
Anti-rollback
32 monotonic OTP counters, 256 increments each
Attestation
Signed quote over PCRs + device PUF identity (Dilithium-3)
Side-channel
DPA / EM countermeasures
Masked AES and ECC datapaths, random clock jitter on crypto blocks, noise generators around the root of trust, dual-rail logic on critical paths, and mesh-shielded top metal. target
Fault injection
Glitch protection
Voltage-glitch detector, clock-integrity monitor, redundant secure-boot decision logic, and a dual-redundant secure-boot decoder. target
Tamper / probing
Physical hardening
Die shield, scrambled bus, key-encrypted SRAM contents, and PUF-based die-thinning detection. target
04 · Crypto
Cryptographic accelerators
Classical and post-quantum algorithms in hardware, with constant-time
and masked implementations on the hardened paths.
Windowed + independent; plus 1 dedicated security watchdog
07 · Acceleration
AI / DSP & clocking
AI / DSP target
Vector throughput
128 GOPS INT8 / 64 GOPS INT16
Hardware accelerators
MFCC feature extraction, matrix acceleration
Clocking target
Application core clock
up to 400 MHz
Security / ULP core clock
up to 80 MHz
Clock management
On-die PLLs with PLL-based frequency scaling
Always-on domain
Independent RTC oscillator for deep-sleep timing
08 · Power
Power & operating conditions
The active-mode current is a preliminary target at 400 MHz and will
be confirmed at silicon characterization. The power-management unit
resides on the always-on island and is controlled exclusively by
the secure world.
Recommended operating conditions target
Parameter
Min
Typ
Max
Unit
Supply voltage (VDD)
3.0
3.3
3.6
V
Operating temperature (industrial)
−40
—
+105
°C
Power consumption (typical) target
State
Typical current
Wake source
Active, 400 MHz
38 mA
—
Modem-sleep (Wi-Fi)
1.2 mA
Radio
Light-sleep
230 µA
RTC, GPIO
Deep-sleep (RTC retained)
30 µA
RTC, GPIO
Hibernation
5 µA
GPIO only
Tx peak, 2.4 GHz +20 dBm
240 mA
—
09 · Package
Package, process & quality
Process suppliers are not named on this website: the U.S.
manufacturing path is under evaluation and supplier commitments are
published only when agreements and validation milestones support
them.
AEC-Q100 Grade 2 — design target, not yet qualified
Defect rate
DPPM < 50 — target
Cryptographic validation scope
FIPS 140-3 — targeted validation scope, not yet validated
Extended-temperature variant
−55 °C to +125 °C — planned variant
10 · Limits
Absolute maximum ratings
Absolute maximum ratings are stress ratings only; operation at or
beyond these limits is not implied and may cause permanent damage.
Absolute maximum ratings target
Parameter
Min
Max
Unit
Supply voltage (VDD)
−0.3
3.9
V
Voltage on any I/O pin
−0.3
VDD + 0.3
V
Storage temperature
−65
+150
°C
ESD (HBM)
—
±2000
V
ESD (CDM)
—
±500
V
Positioning
Against the ESP32-class default.
This is a positioning comparison, not a benchmark. A spec-by-spec
comparison table will be published when silicon-validated data
exists to support one.
Positioning comparison
Dimension
Typical ESP32-class part
MCN-1 direction
Developer experience
Mature ecosystem, huge adoption, the default choice
Same adoption path: open SDK, examples, and migration guides, staged as they are ready